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brainmsp430 [2016/01/16 16:23] – admin | brainmsp430 [2019/08/06 15:11] (current) – admin |
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{1,15,14,13,12,11,10,9,8,7,6,5,4,7,6,5,4,6,5,4,5,6,7,8,9,10,11,12,13,14,15,}, | {1,15,14,13,12,11,10,9,8,7,6,5,4,7,6,5,4,6,5,4,5,6,7,8,9,10,11,12,13,14,15,}, |
{1,14,13,15,12,11,14,11,10,9,11,9,8,7,10,7,6,5,7,6,8,5,8,7,9,11,10,12,}, | {1,14,13,15,12,11,14,11,10,9,11,9,8,7,10,7,6,5,7,6,8,5,8,7,9,11,10,12,}, |
{1,12,14,11,13,12,10,9,8,7,6,5,4,8,7,6,5,4,7,6,5,4,7,6,5,4,5,6,7,8,9,12,10,11,12,15,12,15,12,}, | {1,15,14,13,12,14,11,10,9,8,11,10,9,8,9,8,9,10,8,10,9,8,9,10,11,12,13,10,15,10,11,10,11,12}, |
{1,12,14,11,13,12,10,9,8,7,6,5,4,8,7,6,5,4,7,6,5,4,7,6,5,4,5,6,7,8,9,12,10,11,12,15,12,15,12,}, | {1,12,14,11,13,12,10,9,8,7,6,5,4,8,7,6,5,4,7,6,5,4,7,6,5,4,5,6,7,8,9,12,10,11,12,15,12,15,12,}, |
{1,12,14,11,13,12,10,9,8,7,6,5,4,8,7,6,5,4,7,6,5,4,7,6,5,4,5,6,7,8,9,12,10,11,12,15,12,15,12,}, | {1,12,14,11,13,12,10,9,8,7,6,5,4,8,7,6,5,4,7,6,5,4,7,6,5,4,5,6,7,8,9,12,10,11,12,15,12,15,12,}, |
}; | }; |
const unsigned int brainDuration[8][63] = { | const unsigned int brainDuration[8][63] = { |
{1,20,20,20,20,20,20,20,30,30,30,30,40,5,10,20,40,5,10,30,5,5,5,5,5,5,5,5,5,5,25,}, | {0,20,20,20,20,20,20,20,30,30,30,30,40,5,10,20,40,5,10,30,5,5,5,5,5,5,5,5,5,5,25,}, |
{2,15,15,5,15,15,5,15,15,15,5,15,15,15,3,15,10,10,5,10,5,10,5,10,10,5,15,15,}, | {1,15,15,5,15,15,5,15,15,15,5,15,15,15,3,15,10,10,5,10,5,10,5,10,10,5,15,15,}, |
| {2,15,15,15,15,10,20,20,20,20,5,5,10,10,10,10,10,10,10,5,10,10,10,20,20,20,20,10,15,10,10,10,10,30,}, |
{3,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, | {3,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, |
{4,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, | {4,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, |
{5,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, | {5,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, |
{6,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, | {6,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, |
{7,5,15,10,5,10,8,10,10,12,5,4,15,5,5,10,10,10,5,5,5,10,15,5,5,5,5,5,5,10,10,10,5,5,15,5,10,5,25,}, | {7,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,}, |
{8,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,} | |
}; | }; |
const unsigned int ArrayLength[8] = {31,28,39,39,39,39,39,39,}; | const unsigned int ArrayLength[8] = {31,28,34,39,39,39,39,39,}; |
volatile unsigned int on = 0; | volatile unsigned int on = 0; |
// Declaration of functions | // Declaration of functions |
IFG1 &= ~WDTIFG; | IFG1 &= ~WDTIFG; |
IE1 |= WDTIE; // Enable WDT interrupt | IE1 |= WDTIE; // Enable WDT interrupt |
P1DIR |= 0x0F; // Set P1.0 - P1.3 as output P1.4 - P1.7 as input | P1SEL = 0x00; // Set all Pins to GPIO Pins, no clock sources, nothing |
| P1SEL2 = 0x00; // Set all Pins to GPIO Pins, no clock sources, nothing |
| P2SEL = 0x00; |
| P2SEL2 = 0x00; |
| P3SEL = 0x00; |
| P3SEL2 = 0x00; |
| P1DIR = 0xCF; // Set P1.0 - P1.3 as output P1.4 - P1.5 as input and P1.6 - P1.7 as output |
P1REN = 0x30; // Set P1.4 - P1.5 pull down resistor | P1REN = 0x30; // Set P1.4 - P1.5 pull down resistor |
P1OUT &= 0x00; // Set P1.0 - P1.7 to 0 | P1OUT = 0x00; // Set P1.0 - P1.7 to 0 |
P2DIR &= 0x00; // Set P2.0 - P2.7 as Intput | P2DIR = 0xF8; // Set P2.0 - P2.2 as Intput and P2.3 - P2.7 as Output |
P2REN = 0x07; // Set P2.0 - P2.2 pull down resistor | P2REN = 0x07; // Set P2.0 - P2.2 pull down resistor |
P2OUT &= 0x00; // Set P2.0 - P2.7 to 0 | P2OUT = 0x00; // Set P2.0 - P2.7 to 0 |
| P3DIR = 0xFF; |
| P3OUT = 0x00; |
// Timer_A | // Timer_A |
TA0CCR0 = 1250; // Count limit for 400Hz at !MHz (1000000 / 400 / 2) | TA0CCR0 = 1250; // Count limit for 400Hz at !MHz (1000000 / 400 / 2) |
} | } |
else{ | else{ |
P1OUT &= 0x00; | P1DIR = 0xFF; // Set P1.0 - P1.7 as output |
P1OUT &= 0x00; | P2DIR = 0xFF; // Set P2.0 - P2.7 as output |
_BIS_SR(LPM3_bits); | P1OUT = 0x00; |
| P2OUT = 0x00; |
| __dint(); |
| _BIS_SR(LPM4_bits); |
} | } |
} | } |
P1OUT ^= 0x08; // Toggle output P1.3 | P1OUT ^= 0x08; // Toggle output P1.3 |
} | } |
| |
</code> | </code> |